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1 cat24c208 8k (1k x 8) -bit dual port serial eeprom for vesa plug and play applications in lcd projectors and monitors features 400 khz i 2 c bus compatible* complies with vesa e-edid, e-ddc, di-ext and m1 specifications 3v to 5.5v volt operation low power cmos technology 16-byte page write buffer self-timed write cycle with auto-clear 1,000,000 program/erase cycles 100 year data retention 8-pin dip, soic, tssop or msop packages - green package option industrial and extended temperature ranges description the cat24c208 is an 8k-bit dual port serial cmos eeprom internally organized as 1k words of 8 bits each. the cat24c208 features a 16-byte page write buffer and can be accessed from either of two separate i 2 c compatible ports, dsp (sda, scl) and ddc (sda, scl) which conform to the vesa e-edid eeprom standard. arbitration between the two interface ports is automatic and allows the appearance of individual access to the memory from each interface. using catalyst's advanced cmos technology which substantially reduces device power requirements, the cat24c208 can be powered from either of two independent v cc inputs. the cat24c208 operates over the full industrial and extended temperature range and is available in miniature 8-pin dip, soic, tssop and msop packages. ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice doc. no. 1044, rev. d advance information h a l o g e n f r e e tm l e a d f r e e block diagram * catalyst semiconductor is licensed by philips corporation to carry the i 2 c bus protocol. dsp v cc ddc v cc arbitration logic display control logic ddc control logic configuration register d e c o d e r s d e c o d e r s 1k x 8 memory array edid sel dsp scl dsp sda v ss ddc scl ddc sda
cat24c208 2 doc. no. 1044, rev. d pin configuration dip package (p, l) soic package (j, w) tssop package (u, y) msop package (r, z) pin description 1 2 3 4 8 7 6 5 dsp v cc dsp scl dsp sda v ss ddc v cc edid sel ddc scl ddc sda 8 7 6 5 1 2 3 4 dsp v cc dsp scl dsp sda v ss ddc v cc edid sel ddc scl ddc sda 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 v ss dsp v cc dsp scl dsp sda dsp v cc dsp scl dsp sda v ss ddc v cc edid sel ddc scl ddc sda ddc v c c edid se l ddc scl ddc sda r e b m u n n i pe m a n n i pn o i t c n u f 1v p s d c c r e l l o r t n o c y a l p s i d m o r f r e w o p e c i v e d 2l c s p s d l l a k c o l c o t d e s u s i n i p l a n o i t c e r i d i b k c o l c l a i r e s p s d 8 0 2 c 4 2 t a c e h t o t d e s u o s l a s i d n a n i p a d s p s d e c i v e d e h t f o t u o r o o t n i s r e f s n a r t a t a d . e v i t c a s i t r o p c d d n e h w s s e c c a t r o p p s d k c o l b 3a d s p s d n i p s s e r d d a / a t a d l a i r e s p s d l a n o i t c e r i d i b e h t . s s e r d d a / a t a d l a i r e s p s d y a l p s i d a m o r f e c i v e d e h t f o t u o d n a o t n i a t a d r e f s n a r t o t d e s u s i - e r i w e b n a c d n a t u p t u o n i a r d n e p o n a s i n i p a d s p s d e h t . r e l l o r t n o c . s t u p t u o r o t c e l l o c n e p o r o n i a r d n e p o r e h t o h t i w d e ' r o 4v s s . d n u o r g e c i v e d 5a d s c d d s s e r d d a / a t a d l a i r e s c d d l a n o i t c e r i d i b e h t . s s e r d d a / a t a d l a i r e s c d d . t s o h c d d a m o r f e c i v e d e h t f o t u o d n a o t n i a t a d r e f s n a r t o t d e s u s i n i p h t i w d e ' r o - e r i w e b n a c d n a t u p t u o n i a r d n e p o n a s i n i p a d s c d d e h t . s t u p t u o r o t c e l l o c n e p o r o n i a r d n e p o r e h t o 6l c s c d d l l a k c o l c o t d e s u s i n i p l a n o i t c e r i d i b k c o l c l a i r e s c d d 8 0 2 c 4 2 t a c e h t o t d e s u s i d n a , n i p a d s c d d e c i v e d e h t f o t u o r o o t n i s r e f s n a r t a t a d . e v i t c a s i t r o p p s d n e h w s s e c c a r o f t r o p c d d k c o l b 7l e s d i d e k n a b e v i t c a e h t s t c e l e s t u p n i t c e l e s d i d e 8 0 2 c 4 2 t a c e h t . t c e l e s d i d e n i t e s s a e c a f r e t n i l c s / a d s c d d e h t a i v d e s s e c c a e b o t y r o m e m f o . r e t s i g e r n o i t a r u g i f n o c e h t 8v c d d c c . t s o h c d d a m o r f d e r e w o p n e h w r e w o p e c i v e d
cat24c208 3 doc. no. 1044, rev. d absolute maximum ratings* temperature under bias .................. -55 c to +125 c storage temperature ........................ -65 c to +150 c voltage on any pin with respect to ground (1) ............ -2.0v to +v cc + 2.0v v cc with respect to ground ................ -2.0v to +7.0v package power dissipation capability (t a = 25 c) ................................... 1.0w lead soldering temperature (10 secs) ............ 300 c output short circuit current (2) ........................ 100ma *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. reliability characteristics symbol parameter reference test method min typ max units n end (3) endurance mil-std-883, test method 1033 1,000,000 cycles/byte t dr (3) data retention mil-std-883, test method 1008 100 years v zap (3) esd susceptibility mil-std-883, test method 3015 4000 volts i lth (3)(4) latch-up jedec standard 17 100 ma d.c. operating characteristics v cc = 3v to 5.5v, unless otherwise specified. note: (1) the minimum dc input voltage is C 0.5v. during transitions, inputs may undershoot to C 2.0v for periods of less than 20 ns. maximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc + 2.0v for periods of less than 20ns. (2) output shorted for no more than one second. no more than one output shorted at a time. (3) this parameter is tested initially and after a design or process change that affects the parameter. (4) latch-up protection is provided for stresses up to 100 ma on address and data pins from C 1v to v cc +1v. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tn i mp y tx a ms t i n u i c c t n e r r u c y l p p u s r e w o pf l c s z h k 0 0 1 =3a m i b s v ( t n e r r u c y b d n a t s c c ) v 0 . 5 =v n i r e h t i e r o d n g = v c d d r o p s d c c 0 5a i i l t n e r r u c e g a k a e l t u p n iv n i r e h t i e o t d n g = v c d d r o p s d c c 0 1a i o l t n e r r u c e g a k a e l t u p t u ov t u o r e h t i e o t d n g = v c d d r o p s d c c 0 1a v l i e g a t l o v w o l t u p n i1 C v c c 3 . 0 xv v h i e g a t l o v h g i h t u p n iv c c 7 . 0 xv c c 5 . 0 +v s y h vs i s e r e t s y h t u p n i5 0 . 0v v 1 l o v ( e g a t l o v w o l t u p t u o c c ) v 3 =i l o a m 3 =4 . 0v v 1 l c c v p s d e g a k a e l c c v c d d o t c c + 0 0 1a v 2 l c c v c d d e g a k a e l c c v p s d o t c c + 0 0 1a
cat24c208 4 doc. no. 1044, rev. d the write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. during the write cycle, the bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its slave address. capacitance t a = 25 c, f = 1.0 mhz, v cc = 5v symbol parameter conditions min typ max units c i/o (1) input/output capacitance (either dsp or ddc sda) v i/o = 0v 8 pf c in (1) input capacitance (edid, either dsp or ddc scl) v in = 0v 6 pf note: (1) this parameter is tested initially and after a design or process change that affects the parameter. a.c. characteristics v cc = 3v to 5.5v, unless otherwise specified. read & write cycle limits note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. power-up timing(1)(2) symbol parameter min typ max units t pur power-up to read operation 1 ms t puw power-up to write operation 1 ms l o b m y sr e t e m a r a pn i mx a ms t i n u f l c s y c n e u q e r f k c o l c 0 0 4z h k t i ) 1 ( s t u p n i a d s , l c s t a t n a t s n o c e m i t n o i s s e r p p u s e s i o n 0 0 1s n t a a t u o k c a d n a t u o a t a d a d s o t w o l l c s 1s t f u b ) 1 ( n o i s s i m s n a r t w e n a e r o f e b e e r f e b t s u m s u b e h t e m i t t r a t s n a c 2 . 1s t a t s : d h e m i t d l o h n o i t i d n o c t r a t s6 . 0s t w o l d o i r e p w o l k c o l c2 . 1s t h g i h d o i r e p h g i h k c o l c6 . 0s t a t s : u s t r a t s d e t a e p e r a r o f ( e m i t p u t e s n o i t i d n o c t r a t s ) n o i t i d n o c 6 . 0s t t a d : d h e m i t d l o h n i a t a d0s n t t a d : u s e m i t p u t e s n i a t a d0 5s n t r ) 1 ( e m i t e s i r l c s d n a a d s 3 . 0s t f ) 1 ( e m i t l l a f l c s d n a a d s 0 0 3s n t o t s : u s e m i t p u t e s n o i t i d n o c p o t s6 . 0s t h d e m i t d l o h t u o a t a d0 0 1s n write cycle limits symbol parameter min typ max units t wr write cycle time 5 ms
cat24c208 5 doc. no. 1044, rev. d functional description the cat24c208 has a total memory space of 1k bytes which is accessible from either of two i 2 c interface ports, (dsp_sda and dsp_scl) or (ddc_sda and ddc_scl), and with the use of segment pointer at address 60h. on power up and after any instruction, the segment pointer will be in segment 00h for dsp and in segment 00h of the bank selected by the configuration register for ddc. the entire memory appears as contiguous memory space from the perspective of the display interface (dsp_sda and dsp_scl), see table 2, and figures 11 to figure 18 for a complete description of the dsp interface. a configuration register at addresses 62/63h is used to configure the operation and memory map of the device as seen from the ddc interface, (ddc_sda and ddc_scl). read and write operations can be performed on any location within the memory space from the display dsp interface regardless of the state of the edid sel pin or the activity on the ddc interface. from the ddc interface, the memory space appears as two 500 byte banks of memory, with 2 segments each 00h and 01h in the upper and lower bank, see table 1. each bank of memory can be used to store an e-edid data structure. however, only one bank can be read through the ddc port at a time. the active bank of memory (that is, the bank that appears at address a0h on the ddc port) is controlled through the configuration register at 62/63h and the edid_sel pin. no write operations are possible from the ddc interface unless the ddc write enable bit is set (we = 1) in the device configuration register at device address 62h. the device automatically arbitrates between the two interfaces to allow the appearance of individual access to the memory from each interface. in a typical e-edid application the edid_sel pin is usually connected to the analog cable detect pin of a vesa m1 compliant, dual-mode (analog and digital) display. in this manner, the e-edid appearing at ad- dress a0h on the ddc port will be either the analog or digital e-edid, depending on the state of the analog cable detect pin (pin c3 of the m1-da connector). see figure 1. figure 1. to host controller m1-da connector 28 27 8 hpd fuse, resistor or other current limiting device required in all m1 displays 2a max relay contacts shown in de-energized position e-edid eeprom 8 7 6 5 ddc +5v ddc clk ddc data 26 c3 47.5k 10k 1 2 3 4 i2c to projector/monitor display controller +5v dc (supplied by display) segment 1 256 bytes segment 0 256 bytes segment 1 256 bytes segment 0 256 bytes segment 3 256 bytes segment 2 256 bytes segment 1 256 bytes segment 0 256 bytes 01 00 01 00 11 10 01 00 00 00 00 segment pointer no segment pointer segment pointer no segment pointer lower bank upper bank address by configuration register (see figure 19) memory array memory array table 1: ddc interface table 2: dsp interface
cat24c208 6 doc. no. 1044, rev. d i 2 c bus protocol the following defines the features of the i 2 c bus protocol: (1) data transfer may be initiated only when the bus is not busy. (2) during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock line is high will be interpreted as a start or stop condition. start condition the start condition precedes all commands to the device, and is defined as a high to low transition of either sda when the respective scl is high. the cat24c208 monitors the sda and scl lines and will not respond until this condition is met. stop condition a low to high transition of sda when scl is high determines the stop condition. all operations must end with a stop condition. acknowledge after a successful data transfer, each receiving device is required to generate an acknowledge. the acknowledging device pulls down the respective sda line during the ninth clock cycle, signaling that it received the 8 bits of data. the cat24c208 responds with an acknowledge after receiving a start condition and its slave address. if the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. when the cat24c208 is in a read mode it transmits 8 bits of data, releases the respective sda line, and monitors the line for an acknowledge. once it receives this acknowledge, the cat24c208 will continue to transmit data. if no acknowledge is sent by the master, the device terminates data transmission and waits for a stop condition. after an unsuccessful data transfer an acknowledge will not be issued (nack) by the slave (cat24c208), and the master should abort the sequence. if continued the device will read from or write to the wrong address in the two instruction format with the segment pointers. figure 2. acknowledge timing acknowledge 1 start scl from master 89 data output from transmitter data output from receiver
cat24c208 7 doc. no. 1044, rev. d device addressing ddc interface both the ddc and dsp interfaces to the device are based on the i 2 c bus serial interface. all memory space operations are done at the a0/a1 ddc address pair. as such, all write operations to the memory space are done at ddc address a0h and all read operations of the memory space are done at ddc address a1h. figure 3 shows the bit sequence of a random read from anywhere within the memory space. the word offset determines which of the 256 bytes within segment 00h is being read. here the segment 00h can be at the lower or upper bank depending on the configuration register. sequential reads can be done in much the same manner by reading successive bytes after each acknowledge without generating a stop condition. see figure 4. the device automatically increments the word offset value (8-bit value) and with wraparound in the same segment 00h to read maximum of 256 bytes. figure 3. random access read (segment 00h only) figure 4. sequential read (segment 00h only) t r a t s0 0 0 0 0 1 0 1k c as s e r d d a 0 a - 7 ak c at r a t s1 0 0 0 0 1 0 1k c aa t a dk c a o np o t s t r a t s0 0 0 0 0 1 0 1k c a 0 a - 7 a s s e r d d a k c at r a t s1 0 0 0 0 1 0 1k c a0 a t a dk c a. . . . . . . . .n a t a dk c a o np o t s figures 5 and 6 show the byte and page write respectively. the configuration register must have the we bit set to 1 prior to any write on ddc port. only the segment 00h can be accessed of either lower or upper bank. figure 5. byte write (segment 00h only) t r a t s0 0 0 0 0 1 0 1k c as s e r d d a 0 a - 7 ak c aa t a dk c ap o t s figure 6. page write (segment 00h only) t r a t s0 0 0 0 0 1 0 1k c as s e r d d a 0 a - 7 ak c a0 a t a dk c a. . . . . . . . .5 1 a t a dk c ap o t s word offset word offset word offset word offset
cat24c208 8 doc. no. 1044, rev. d figure 7. random access read t r a t s0 0 0 0 0 1 1 0k c as x x x x x x 1 s 0 s s e r d d a t n e m g e sk c a t r a t s0 0 0 0 0 1 0 1k c as s e r d d a 0 a - 7 ak c at r a t s1 0 0 0 0 1 0 1k c aa t a dk c a o np o t s figure 8. sequential read t r a t s0 0 0 0 0 1 1 0k c as x x x x x x 1 s 0 s s e r d d a t n e m g e sk c a t r a t s0 0 0 0 0 1 0 1k c as s e r d d a 0 a - 7 ak c at r a t s1 0 0 0 0 1 0 1k c a0 a t a dk c a. . . . . .n a t a dk c a o np o t s figure 9. byte write t r a t s0 0 0 0 0 1 1 0k c as x x x x x x 1 s 0 s s e r d d a t n e m g e sk c a t r a t s0 0 0 0 0 1 0 1k c as s e r d d a 0 a - 7 ak c aa t a dk c ap o t s figure 10. page write t r a t s0 0 0 0 0 1 1 0k c as x x x x x x 1 s 0 s s e r d d a t n e m g e sk c a t r a t s0 0 0 0 0 1 0 1k c as s e r d d a 0 a - 7 ak c a0 a t a dk c a. . . . . . . . . .5 1 a t a dk c ap o t s the segment pointer is at the address 60h and is write-only. this means that a memory access at 61h will give undefined results. the segment pointer is a volatile register. the device configuration register at 62/63 (hex) is a non-volatile register. the configuration register will be shipped in the erased (set to ffh) state. the segment pointer is used to expand the available ddc address space while maintaining backward compatibility with older ddc interfaces such as ddc2b. for each value of the 8-bit segment pointer one segment (256 bytes) is available at the a0/a1 pair. the standard ddc 8-bit address is sufficient to address each of the 256 bytes within a segment. note that if the segment pointer is set to 00h then the device will behave like a standard ddc2b eeprom. read and write with segment pointer can expand the addressable memory to 512 bytes in each bank with wraparound to the next segment in the same bank only. the two banks can be individually selected by the configuration register and edid sel pin, as shown in figure 19. the segments are selected by the two bits s 1 s 0 = 00 or 01 in the segment address. figures 7 to 10 show the random read, sequential read, byte write and page write.
cat24c208 9 doc. no. 1044, rev. d dsp interface the dsp interface is similar to i 2 c bus serial interface. without the segment pointer, the maximum accessible memory space is 256 bytes of segment 00h only. in the sequential mode the wrap around will be in the same segment also. figures 11 to 14 show the read and write on the dsp port. figure 15. random access read t r a t s0 0 0 0 0 1 0 1k c as s e r d d a 0 a - 7 ak c at r a t s1 0 0 0 0 1 0 1k c aa t a dk c a o np o t s figure 12. sequential read figure 17. byte write figure 14. page write t r a t s0 0 0 0 0 1 0 1k c as s e r d d a 0 a - 7 ak c at r a t s1 0 0 0 0 1 0 1k c a0 a t a dk c a. . . . .n a t a dk c a o np o t s t r a t s0 0 0 0 0 1 0 1k c as s e r d d a 0 a - 7 ak c aa t a dk c ap o t s t r a t s0 0 0 0 0 1 0 1k c as s e r d d a 0 a - 7 ak c a0 a t a dk c a. . . . . .5 1 a t a dk c ap o t s the segment pointer is used to expand the available dsp port addressable memory to 1k bytes, divided into four segments of 256 bytes each. the four segments are selected by two bits s 1 s 0 = 00, 01, 10, 11 in the segment address. figures 15 to 18 show the random read, sequential read, byte write and page write. figure 11. random access read figure 16. sequential read figure 13. byte write figure 18. page write t r a t s0 0 0 0 0 1 1 0k c as x x x x x x 1 s 0 s s e r d d a t n e m g e sk c a t r a t s0 0 0 0 0 1 0 1k c as s e r d d a 0 a - 7 ak c at r a t s1 0 0 0 0 1 0 1k c aa t a dk c a o np o t s t r a t s0 0 0 0 0 1 1 0k c as x x x x x x 1 s 0 s s e r d d a t n e m g e sk c a t r a t s0 0 0 0 0 1 0 1k c as s e r d d a 0 a - 7 ak c at r a t s1 0 0 0 0 1 0 1k c a0 a t a dk c a. . . . . . .n a t a dk c a o np o t s t r a t s0 0 0 0 0 1 1 0k c as x x x x x x 1 s 0 s s e r d d a t n e m g e sk c a t r a t s0 0 0 0 0 1 0 1k c as s e r d d a 0 a - 7 ak c a0 a t a dk c a. . . . . .5 1 a t a dk c ap o t s t r a t s0 0 0 0 0 1 1 0k c as x x x x x x 1 s 0 s s e r d d a t n e m g e sk c a t r a t s0 0 0 0 0 1 0 1k c as s e r d d a 0 a - 7 ak c aa t a dk c ap o t s
cat24c208 10 doc. no. 1044, rev. d configuration register function description: nb: number of memory banks in ddc port memory map. 0 = 2 banks, 1 = 1 bank ab0: active bank control bit 0 (see figure 19) ab1: active bank control bit 1 (see figure 19) we ddc: write enable 0 = write disabled, 1= write enabled note: we affects only write operations from the ddc port, not the display port. the display port always has write access. figure 19. configuration register truth table arbitration the device performs a simplistic arbitration between the ddc and display interfaces. while the arbitration scheme described is not foolproof, it does prevent most errors. the arbitration logic uses clock stretching , an i 2 c bus term, to hold off writes from one port while the other port is active. arbitration logic within the device monitors activity on ddc_scl and dsp_scl. when both i2c ports are idle, ddc_scl and dsp_scl are both high and the arbitration logic is inactive. when either ddc_scl or dsp_scl is pulled low, initiating a read or write, the arbitration logic pulls down the other scl line and holds it low, holding off activity on the other port (by stretching the clock on that port). when the initiating scl line has remained high for one full second, the arbitration logic assumes that the initiating devices is finished and releases the other scl line. if the non-initiating device has been waiting for access, it can now read or write the device. for this scheme to work properly, both the ddc and dsp devices must properly implement clock stretching as defined by the i 2 c specification. additionally, it is very important that when writing to the device that the scl line never remains high longer than 1 second, until the write is complete. this prevents the other port from having access until the device is fully written. 1 b a0 b ab n d i d e n i p t c e l e s k n a b e v i t c a 0x 0 0 k n a b r e w o l 0x 0 1 k n a b r e p p u 10 0 x k n a b r e w o l 11 0 x k n a b r e p p u xx 1 x k n a b ) y l n o ( r e w o l the configuration register is a non-volatile register and is available from either dsp or ddc port at address 62h/63h for write and read resp. figure 20. read configuration register figure 21. write configuration register t r a t s0 1 0 0 0 1 1 0k c as s e r d d a y m m u dk c ab n 0 b a 1 b a e w x x x xk c ap o t s t r a t s1 1 0 0 0 1 1 0k c aa t a dk c a o np o t s n o i t c n u f r e t s i g e r b s mb s l 76543 2 10 r e t s i g e r n o i t a r u g i f n o c xxxx e w1 b a0 b ab n
cat24c208 11 doc. no. 1044, rev. d notes: (1) the device used in the above example is a cat24c208ji-te13 (soic, industrial temperature, 3 volt to 5.5 volt operating voltage, tape & reel) ordering information prefix device # suffix 24c208 j i te13 product number 24c208: 8k tape & reel package p: pdip j: soic (jedec) u: tssop cat temperature range i = industrial (-40 to 85 c) optional company id r: msop l: pdip (lead free, halogen free) w: soic (lead free, halogen free) y: tssop (lead free, halogen free) z: msop (lead free, halogen free) e = extended (-40 to 125 c)
cat24c208 12 doc. no. 1044, rev. d 0.180 (4.57) max 0.015 (0.38) 0.100 (2.54) bsc 0.014 (0.36) 0.022 (0.56) d 0.245 (6.17) 0.295 (7.49) 0.045 (1.14) 0.060 (1.52) 0.110 (2.79) 0.150 (3.81) 0.120 (3.05) 0.150 (3.81) 0.300 (7.62) 0.325 (8.26) 0.310 (7.87) 0.380 (9.65) dimension d pkg min max 8l 0.355 (9.02) 0.400 (10.16) packaging information 8 lead pdip (p, l)
cat24c208 13 doc. no. 1044, rev. d packaging information 8 lead 150 mil wide soic (j, w) 0.149 (3.80) 0.1574 (4.00) 0.2284 (5.80) 0.2440 (6.20) 0.0532 (1.35) 0.0688 (1.75) 0.0040 (0.10) 0.0098 (0.25) 0.050 (1.27) bsc 0.013 (0.33) 0.020 (0.51) 0.0099 (0.25) 0.0196 (0.50) 0.0075 (0.19) 0.0098 (0.25) 0.016 (0.40) 0.050 (1.27) 0 ? -8 ? x 45 ? 0.1890 (4.80) 0.1968 (5.00) notes: 1. complies with jedec publication 95 ms-012 dimensions; however, some dimensions may be more stringent. 2. all linear dimensions are in inches and parenthetically in millimeters. 3. lead coplanarity is 0.004" (0.102mm) maximum.
cat24c208 14 doc. no. 1044, rev. d packaging information 8 lead tssop (u, y) notes: 1. lead coplanarity is 0.004" (0.102mm) maximum.
cat24c208 15 doc. no. 1044, rev. d 0.0150 0.0110 0.38 0.28 0.1970 0.1890 5.00 4.80 s 0.0256 [0.65] bsc 0.1220 0.1142 3.10 2.90 0.0433 [1.10] max. 0.039 [0.10] max. s 0.0059 0.0020 0.15 0.05 s 0.0374 0.0295 0.95 0.75 0.0276 0.0157 0.70 0.40 0.1220 0.1142 3.10 2.90 0 ? - 6 ? 0.0091 0.0051 0.23 0.13 0.0118 [0.30] ref. base metal 0.0050 [0.127] 0.0150 0.0110 0.38 0.28 with plating section a - a with plating packaging information 8 lead msop (r, z)
catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catalyst-semiconductor.com publication #: 1044 revison: d issue date: 03/25/05 type: advance copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the companys corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. revision history date rev. reason 2/18/2004 c changed volt operation to 3v to 5.5v updated block diagram updated pin descriptions updated dc operating characteristics updated ac characteristics changed/added figures 3 - 21 updated ordering information 03/25/2005 d updated function description updated oedering information

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